Field programmable gate arrays (FPGAs) are popular platforms for implementing cryptography functions in networking, storage, and blockchain applications, for example. FPGAs provide convenient software control and ease of adding and/or improving functions.
Though FPGAs can be advantageous for implementations of cryptography systems, FPGAs present design challenges. Implementations of cryptography functions can consume a large quantity of FPGA resources such as look-up tables (LUTs), flip-flops (FFs), and block random access memories (BRAMs). For example, a single media access control security function (MACsec) can consume approximately 100,000 LUTs, approximately 100,000 FFs, and approximately 100 BRAMs. The large quantity of FPGA resources can challenge the circuit designer in closing timing on the circuit design, depending on the target clock speed. To alleviate timing issues, extensive pipelining may be employed, which can lead to the implemented circuit consuming more power than is desirable.